Valtrix joins RISC-V International
Nov 4, 2020. | By: Shubhodeep Roy Choudhury
I am proud to announce that
Valtrix has joined
RISC-V International, a global non-profit organization aiming to promote and democratize the open source RISC-V instruction set architecture.
Valtrix is an EDA startup developing solutions for functional verification of SoC/CPU implementations. We also provide engineering
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Importance of Software Driven Functional Verification Methodology
Sep 5, 2020. | By: Shubhodeep Roy Choudhury
A good functional verification methodology is extremely crucial to the success of any semiconductor design project. Missed or late bugs can massively hurt market share, revenue and brand name even for reputed companies. The complexity of SoC designs along with tight time-to-market constraints demand high levels of efficiency in the verification process.
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Using STING Release Packages for Verifying RISC-V Implementations
Oct 25, 2019. | By: Shubhodeep Roy Choudhury
This blog provides an overview of
STING’s release mode of operation. STING design verification tool is released to the end user in form of a self extracting script. The script can be used to install the release package in user’s environment. Once the package is installed, the user needs to set few environment variables before the STING executable
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Valtrix at the 8th RISC-V Workshop Barcelona May 2018
Apr 17, 2018. | By: Shubhodeep Roy Choudhury
Valtrix will participate in the
8th RISC-V workshop at Barcelona, Spain in May 2018. Co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) and sponsored by NXP and Western Digital, this event will
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Running STING on PULPino Platform
Dec 18, 2017. | By: Shubhodeep Roy Choudhury
PULPino is a competitive, state-of-the-art 32-bit processor based on the RISC-V architecture, with a rich set of peripherals, and full debug support developed at ETH Zurich and Università di Bologna. PULPino is based on optimized 32-bit RISC-V cores (known as RI5CY and Zero-riscy) with complete support for the RV32I base integer instruction
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Test Plans for RISC-V CPU Specification
Nov 10, 2017. | By: Shubhodeep Roy Choudhury
We now have test plans for the
RISC-V user level and privileged specifications. All the test scenarios and conditions are covered in
STING’s RISC-V verification suite. Test plan extensions for other IP(s) in the RISC-V based SoC can also be easily developed.
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Support for Accellera's Upcoming Portable Stimulus Specification in STING
Oct 2, 2016. | By: Shubhodeep Roy Choudhury
I went to the 2016 edition of
DVCON India last month. Since Valtrix is also working in the area of reusable and portable stimulus, I attended the Accellera update on PSWG. You can read more about Accellera’s Portable Stimulus Working Group
here in case you are not aware of the ongoing effort. Speakers from Mentor Graphics,
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Profiling Performance Monitoring Events for STING's Test Stimulus on Qualcomm Dragonboard 410C
Jun 20, 2016. | By: Shubhodeep Roy Choudhury
On successfully
enabling STING on Qualcomm Dragonboard 410C board, the quality of test stimulus generated by STING was evaluated by profiling the performance monitoring events available in the CPU implementation. As part of this exercise, few open source benchmarks were also profiled for the same set of events and the results
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Announcing Support for RISC-V in STING
May 30, 2016. | By: Shajid T
Valtrix Systems is happy to announce the availability of
STING for
RISC-V architecture. RISC-V is an open-source instruction set architecture (ISA) based on reduced instruction set computing (RISC) fundamentals. It has been designed to support extensive customization and specialization across multiple classes
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Programming ARM v8 Performance Monitors
May 25, 2016. | By: Shubhodeep Roy Choudhury
Verification engineers often need a measure for the quality of the test stimulus being generated.
Is the instruction sequence generated by a test configuration for cache eviction really meeting its intent? How do we find if no coverage is being generated after a recent source commit in the test generator tool? How does your test program fare against
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Enabling Baremetal Multiprocessor Code on Qualcomm Dragonboard 410C
Feb 26, 2016. | By: Shajid T
Ever since the initial product development milestones of
STING were met, I have been trying to enable it on a real silicon. Lot of 64-bit ARMv8 based systems/boards have released in last few quarters. We selected Qualcomm Dragonboard 410C for the bringup activity as it would give an access to 64-bit ARMv8 CPUs in addition to other
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A Lightweight Function Entry and Exit Profiler
Oct 23, 2015. | By: Shubhodeep Roy Choudhury
Recently, I had been working on a framework for logging of debug and information messages in
STING. STING messages contain lot of information related to test generation and debug which are important for the developer and debugger. Since the code base is quite huge, it is essential to improve the clarity of the messages by annotating them
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Introducing Valtrix Systems
Oct 7, 2015. | By: Shubhodeep Roy Choudhury
Valtrix Systems is a startup delivering innovative products and solutions for IP/SoC design verification. Our solutions are architected to shift-left the design and verification of complex systems resulting in a faster time-to-market at reduced cost and effort. We also provide consultations and service on different aspects of IP/SoC design
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